1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method for testing the nonvolatile semiconductor memory. In particular, the present invention relates to a nonvolatile semiconductor memory that internally generates a drive voltage for data read and write, and a method for testing the nonvolatile semiconductor memory.
2. Description of Related Art
There have been known nonvolatile semiconductor memories such as a flash memory or an electrically erasable and programmable read only memory (EEPROM). A memory cell of the nonvolatile semiconductor memory of this type has a charge storage layer such as a floating gate. The data write and erase are executed by injecting electrons into the charge storage layer or extracting electrons from the charge storage layer. In this case, there is a need to apply a relatively high voltage to word lines and bit lines.
Problems unique to the nonvolatile semiconductor memory of this type include “write disturb”. The write disturb unit that the high voltage to be applied at the time of writing or erasing data also affects unselected cells, thereby causing data in the affected unselected cells to be rewritten. Accordingly, in a screening process before shipment of products, there is a need to implement a write disturb test on respective chips. Also, in the screening process, the test of other cell characteristics is also implemented.
In the above characteristic test, there is a need to apply an appropriate voltage to the respective memory cells. In general, the nonvolatile internally generates the drive voltage for data read and write. For that purpose, the nonvolatile semiconductor memory is equipped with a voltage generator circuit for generating the drive voltage. For example, the high voltage required for data write and erase is generated by the voltage generator circuit such as a charge pump or a regulator. In testing the characteristics of the nonvolatile semiconductor memory, there is a need to generate an appropriate drive voltage by using the voltage generator circuit.
JP-A-2000-173297 discloses a technique for screening a dynamic random access memory (DRAM). The technique aims at reducing a time necessary for screening. According to the technique, a burn-in test is implemented for screening the DRAM. In the burn-in test, an internal voltage generated within the DRAM is made higher than that in a normal state, thereby reducing a stressing time. As a result, the screening time is reduced. In more detail, the DRAM includes a first step-down power supply unit, a second step-down power supply unit, a step-up power supply unit, a negative power supply unit, and a third step-down power supply unit. The first step-down power supply unit generates a first step-down voltage lower than a supply voltage in a normal state, and outputs the supply voltage in a test state. The second step-down power supply unit generates a second step-down voltage higher than the first step-down voltage in the normal state, and outputs the supply voltage in the test state. The step-up power supply unit generates a step-up voltage higher than the supply voltage in the normal state, and changes a level of the step-up voltage in the test state. The negative power supply unit generates a negative voltage in the normal state, and changes a level of the negative voltage in the test state. The third step-down power supply unit generates a third step-down voltage lower than the first step-down voltage, and changes a level of the third step-down voltage in the test state.